The working below follows the course definitions: chip organisation \(2^{x}\times y\), RAS/CAS address multiplexing, the JEDEC module-name rule \(\mathrm{DDR}X\text{-}Y=\mathrm{PC}X\text{-}Z\), and set-associative cache address fields. Question 4 follows the SK hynix video LPDDR, Evolving to Your Needs.

A DRAM chip has 10 address pins and 8 data pins, together with RAS and CAS pins.

(a) The two components of one DRAM cell

A single DRAM cell is a storage capacitor and an access transistor (a MOSFET switch). The capacitor holds the bit as charge. The transistor connects that capacitor to the bit line only while the word line (row) is asserted.

On a write, the bit-line voltage charges or discharges the capacitor. On a read, the capacitor shares its charge with the bit line; a sense amplifier decides 0 or 1, and the charge is written back because the read is destructive.

(b) Organisation

The course writes a chip’s organisation as \(2^{x}\times y\):

• \(x\) is the number of address bits inside the chip (the number of locations is \(2^{x}\));

• \(y\) is the number of data pins.

RAS/CAS multiplexing sends the address in two halves on the same pins. The row half is strobed by RAS and the column half by CAS. With 10 address pins, \[\frac{x}{2}=10 \quad\Rightarrow\quad x=20.\] The data width is the number of data pins, \(y=8\). Therefore the organisation is \[\textcolor{accent}{\textbf{$2^{20}\times 8$}}.\] There are \(2^{20}=1\,048\,576\) addresses, and each address returns 8 bits.

(c) Capacity

Chip capacity is counted in bits, as the product of the number of locations and the width: \[2^{20}\times 8 = 2^{20}\times 2^{3} = 2^{23} = 8\,388\,608 \text{ bits}.\] \[% \textcolor{accent}{8\ \text{Mbits}} \quad\bigl(2^{23}\text{ bits}\bigr).\] That is \(1\) Mbyte of storage, but the unit required for a memory IC is bits.

Question 2 marks

Module name PC2-6400. Timing \(t_{\mathrm{CL}}\text{-}t_{\mathrm{RCD}}\text{-}t_{\mathrm{RP}}\text{-}t_{\mathrm{RAS}}=2\text{-}7\text{-}9\text{-}10\).

The course naming rule is \[\mathrm{DDR}X\text{-}Y \;=\; \mathrm{PC}X\text{-}Z,\] where \(X\) is the DDR generation, \(Y\) is the pin transfer rate in megatransfers per second, and \(Z\) is the module data rate in MB/s. A standard DIMM is 64 bits \(=8\) bytes wide, so \[Z = Y \times 8.\] DDR2 prefetches 4 bits per memory-clock cycle and still transfers data on both edges of the I/O clock, which gives the relations used below.

(a) Data rate 2 marks

The module name stores \(Z\) directly: \[\mathrm{PC2\text{-}6400} \quad\Rightarrow\quad % \textcolor{accent}{6400\ \mathrm{MB/s}}.\]

(b) Standard name

\[Y = \frac{Z}{8} = \frac{6400}{8} = 800.\] The prefix PC2 means DDR2, so the standard name is \[% \textcolor{accent}{\mathrm{DDR2\text{-}800}}.\]

(c) I/O bus frequency

Data moves on both edges of the I/O clock, so the I/O clock is half the transfer rate: \[f_{\mathrm{I/O}} = \frac{800}{2} = % \textcolor{accent}{400\ \mathrm{MHz}}.\] This matches the course table, where DDR2-1000 has a \(500\,\mathrm{MHz}\) I/O bus.

(d) Memory clock frequency

DDR2’s prefetch is 4, so the internal memory clock is the transfer rate divided by 4: \[f_{\mathrm{mem}} = \frac{800}{4} = % \textcolor{accent}{200\ \mathrm{MHz}}.\] Equivalently, the course factor “2 times” says the I/O bus runs at twice the memory clock: \(400/2=200\,\mathrm{MHz}\).

(e) I/O bus period 2 marks

\[t_{\mathrm{CK}} = \frac{1}{f_{\mathrm{I/O}}} = \frac{1}{400\times 10^{6}} = 2.5\times 10^{-9}\,\mathrm{s} = % \textcolor{accent}{2.5\ \mathrm{ns}}.\] All four timing parameters are counts of this I/O clock: \[\begin{aligned} t_{\mathrm{CL}}&=2, & t_{\mathrm{RCD}}&=7, & t_{\mathrm{RP}}&=9, & t_{\mathrm{RAS}}&=10. \end{aligned}\]

(f) Cycle time for 8 consecutive data words 8 marks

The device has been idle for a long time, so every bank is precharged and the required row is closed. The read therefore starts with an Activate. The question says the page stays open, so the row is not precharged afterwards and \(t_{\mathrm{RP}}\) is not added.

Events, timed by the I/O clock:

1. Activate is issued at clock edge 0. The controller must wait \(t_{\mathrm{RCD}}=7\) cycles before a column command is legal.

2. Read is issued at cycle 7. The first data word is valid \(t_{\mathrm{CL}}=2\) cycles later, at cycle \(7+2=9\).

3. The module is DDR, so two data words leave on each I/O clock (rising edge, then falling edge). Eight words therefore occupy \[\frac{8}{2}=4\] clock cycles of burst time, and the last word is on the falling edge, half a cycle before that burst window ends.

Word \(k\) (counting from 0) is valid at \[t = \bigl(t_{\mathrm{RCD}}+t_{\mathrm{CL}}\bigr)\,t_{\mathrm{CK}} + k\cdot\frac{t_{\mathrm{CK}}}{2}.\] The eighth word is \(k=7\): \[\begin{aligned} t &= \left(7+2+\frac{7}{2}\right)\times 2.5\ \mathrm{ns} = (9+3.5)\times 2.5\ \mathrm{ns} = 12.5\times 2.5\ \mathrm{ns} = % \textcolor{accent}{31.25\ \mathrm{ns}}. \end{aligned}\]

\(t_{\mathrm{RAS}}=10\) cycles \(=25\,\mathrm{ns}\) is the earliest moment at which a Precharge of this row would be allowed. The last word arrives at \(31.25\,\mathrm{ns}\), which is already later than \(t_{\mathrm{RAS}}\), and the question does not close the page. So neither \(t_{\mathrm{RAS}}\) nor \(t_{\mathrm{RP}}\) is added.

Question 3 marks

Both caches are set-associative and byte-addressable. The address splits as \[\underbrace{\text{tag}}_{\text{which block}} \;|\; \underbrace{\text{index}}_{\text{which set}} \;|\; \underbrace{\text{offset}}_{\text{byte in the block}}.\] The parameters are tied together by: \[\begin{align*} \text{offset bits} &= \log_{2}(\text{block size in bytes}),\\ \text{number of sets} &= 2^{(\text{index bits})} = \text{depth},\\ \text{number of blocks} &= \text{sets}\times\text{associativity},\\ \text{capacity} &= \text{number of blocks}\times\text{block size},\\ \text{tag bits} &= \text{address width}-\text{index bits}-\text{offset bits},\\ \text{tag comparisons per request} &= \text{associativity}. \end{align*}\] Depth is the number of sets: the index selects one row of the array, and the degree of associativity is the number of ways in that row. A request compares the incoming tag with every way of the selected set, so the comparison count equals the associativity.

Cache (a)

Given: capacity \(1024\) bytes, associativity \(4\), depth \(32\), tag \(2\) bits.

\[\begin{align*} \text{number of sets} &= \text{depth} = 32,\\ \text{index bits} &= \log_{2} 32 = 5,\\ \text{number of blocks} &= 32\times 4 = 128,\\ \text{block size} &= \frac{1024}{128} = 8\ \text{bytes},\\ \text{offset bits} &= \log_{2} 8 = 3,\\ \text{address width} &= 2+5+3 = 10\ \text{bits},\\ \text{tag comparisons} &= 4. \end{align*}\] Check: \(32\) sets \(\times 4\) ways \(\times 8\) bytes \(=1024\) bytes.

Cache (b)

Given: address width \(20\) bits, block size \(4\) bytes, index \(7\) bits, tag comparisons \(2\).

\[\begin{align*} \text{associativity} &= \text{tag comparisons} = 2,\\ \text{offset bits} &= \log_{2} 4 = 2,\\ \text{tag bits} &= 20-7-2 = 11,\\ \text{depth} &= 2^{7} = 128\ \text{sets},\\ \text{number of blocks} &= 128\times 2 = 256,\\ \text{capacity} &= 256\times 4 = 1024\ \text{bytes}. \end{align*}\]

Completed table

Question 4 marks

Source: SK hynix, LPDDR, Evolving to Your Needs (https://www.youtube.com/watch?v=bVOzGVABUZQ). The video poses “three major advantages” and then develops exactly three technical changes for each generation.

(a) Three advantages of LPDDR4(x) over LPDDR3

1. Two 16-bit channels, with a shorter data and clock path. LPDDR3 is organised as one \(\times 32\) channel. The clock and data routes cross the whole channel, which costs core power and limits speed. LPDDR4(x) splits the same 32-bit width into two independent \(\times 16\) channels (CA_A with DQ byte 0/1, and CA_B with DQ byte 0/1). Each side has a short clock path, so core power falls and the operating rate rises. The video quotes a pin rate of \(4266\,\mathrm{Mbps}\).

2. LVSTL interface and a lower I/O voltage. LPDDR3 uses HSUL12 signalling with \(V_{\mathrm{DDQ}}=1.2\,\mathrm{V}\) and optional on-die termination. LPDDR4(x) switches to Low Voltage Swing Terminated Logic. \(V_{\mathrm{DDQ}}\) drops to \(0.6\,\mathrm{V}\) and termination is the low-voltage kind, so the I/O power rail is lower and the device draws less battery current than LPDDR3. The opening slide also notes that a \(1\mathrm{ynm}\) LPDDR4(x) product uses up to about \(10\%\) less power than the previous generation at \(4266\,\mathrm{Mbps}\).

3. Post-package repair (PPR). After the device is packaged, one failed row per bank can still be replaced. The sequence is guarded by a vendor-specific MR9 key so the chip cannot enter PPR by accident: enter PPR, enable the repair, activate the failed row address, run the row repair, precharge, then disable PPR. Mode registers that were set before the repair are cleared when PPR mode is left. This repairs defects that only show up after packaging, which raises usable yield and field reliability.

(b) Three advantages of LPDDR5 over LPDDR4(x)

1. A separate WCK clock, which raises the data rate to \(6400\,\mathrm{Mbps}\). LPDDR4(x) times commands and data from one CK, and its command/address bus is SDR, with a per-pin rate of \(400\)–\(4266\,\mathrm{Mbps}\). LPDDR5 adds a differential data clock, WCK, that runs at two or four times the command clock CK. CK itself stays at or below \(800\,\mathrm{MHz}\) and is no longer tied to the data strobe. The shorter WCK tree has less jitter, which is what makes \(6.4\,\mathrm{Gbps}\) practical, while the slower command clock burns less active standby power. The video states that \(6400\,\mathrm{Mbps}\) is \(50\%\) faster than the LPDDR4 solutions. The command/address bus also becomes a 7-bit DDR bus with no separate CKE.

2. A flexible bank architecture. LPDDR4(x) has 8 banks per 16-bit channel. LPDDR5 lets the mode register select the organisation that matches the traffic:

   • bank-group mode: 4 banks \(\times\) 4 groups, for rates above \(3200\,\mathrm{Mbps}\), burst length 16 or 32, \(2\,\mathrm{KB}\) pages;

   • 16-bank mode: 16 banks and no groups, for rates up to \(3200\,\mathrm{Mbps}\);

   • 8-bank mode: 8 banks, no groups, burst length 32 only, \(4\,\mathrm{KB}\) pages, across the whole speed range.

   More banks, and bank groups at high speed, let the controller hide row misses by moving to another bank instead of waiting on one.

3. Dynamic voltage and frequency scaling (DVFS). Most real traffic sits at low or mid frequency, so LPDDR5 can drop the supplies only in that region and return to the high rails when the link speeds up. With DVFS-C, part of the peripheral circuitry moves from the \(1.05\,\mathrm{V}\) core rail onto \(V_{\mathrm{DD2L}}=0.9\,\mathrm{V}\). With DVFS-Q, \(V_{\mathrm{DDQ}}\) falls from \(0.5\,\mathrm{V}\) to \(0.3\,\mathrm{V}\). LPDDR4(x) does not have this speed-dependent scaling. The intro slide summarises the result as greater battery efficiency, plus the freedom to set the operating voltage for the speed in use.

The same comparison table in the video also records two supporting reliability changes that sit behind these three: link ECC in addition to on-die ECC, and ZQ calibration that may be started in the background as well as by command.

End of Assignment 1.