Series: RISC V Hardware
bash
47 lines
· Updated 2026-07-04
build.sh
RISC_V_Hardware/build.sh
#!/bin/bash
# ============================================================
# build.sh - compile latex/chapters/*.tex into pdf/*.pdf
# usage:
# ./build.sh build all chapters
# ./build.sh ch01 ch02 build selected chapters
# ============================================================
set -u
ROOT="$(cd "$(dirname "$0")" && pwd)"
SRC="$ROOT/latex/chapters"
OUT="$ROOT/pdf"
TMP="$ROOT/latex/.build"
mkdir -p "$OUT" "$TMP"
if [ $# -gt 0 ]; then
FILES=""
for name in "$@"; do
FILES="$FILES $SRC/${name%.tex}.tex"
done
else
FILES="$SRC"/*.tex
fi
FAIL=0
cd "$SRC"
for f in $FILES; do
base="$(basename "$f" .tex)"
# encoding guard: chapter sources must contain UTF-8 multibyte chars
if ! LC_ALL=C grep -q '[^\x00-\x7F]' "$f"; then
echo "==> $base: ERROR pure-ASCII source (encoding corrupted?), skip"
FAIL=1
continue
fi
echo "==> Building $base"
for pass in 1 2; do
if ! xelatex -interaction=nonstopmode -halt-on-error \
-output-directory="$TMP" "$f" > "$TMP/$base.pass$pass.log" 2>&1; then
echo " FAILED (pass $pass) - see $TMP/$base.pass$pass.log"
FAIL=1
continue 2
fi
done
mv "$TMP/$base.pdf" "$OUT/$base.pdf"
pages=$(pdfinfo "$OUT/$base.pdf" 2>/dev/null | awk '/^Pages:/{print $2}')
echo " OK -> pdf/$base.pdf ($pages pages)"
done
exit $FAIL
Related articles
RISC V Hardware
latex
Updated 2026-07-04
style.tex
style.tex — latex source code from the RISC V Hardware learning materials (RISC_V_Hardware/latex/common/style.tex).
Read article →
RISC V Hardware
verilog
Updated 2026-07-04
alu.v
alu.v — verilog source code from the RISC V Hardware learning materials (RISC_V_Hardware/verilog/rtl/alu.v).
Read article →
RISC V Hardware
verilog
Updated 2026-07-04
branch_unit.v
branch_unit.v — verilog source code from the RISC V Hardware learning materials (RISC_V_Hardware/verilog/rtl/branch_unit.v).
Read article →
RISC V Hardware
verilog
Updated 2026-07-04
control.v
control.v — verilog source code from the RISC V Hardware learning materials (RISC_V_Hardware/verilog/rtl/control.v).
Read article →
RISC V Hardware
verilog
Updated 2026-07-04
dmem.v
dmem.v — verilog source code from the RISC V Hardware learning materials (RISC_V_Hardware/verilog/rtl/dmem.v).
Read article →
RISC V Hardware
verilog
Updated 2026-07-04
imem.v
imem.v — verilog source code from the RISC V Hardware learning materials (RISC_V_Hardware/verilog/rtl/imem.v).
Read article →