tb_trace.v

`timescale 1ns/1ps
module tb_trace;
    reg clk = 0; reg rst_n = 0;
    wire [31:0] dbg_pc;
    top_pipeline #(.MEMFILE("test_dbg.hex")) dut (.clk(clk), .rst_n(rst_n), .dbg_pc(dbg_pc));
    always #5 clk = ~clk;
    integer c;
    initial begin
        rst_n = 0; repeat (2) @(posedge clk); rst_n = 1;
        for (c = 0; c < 40; c = c + 1) begin
            @(negedge clk);
            $display("c=%0d pc=%h if_instr=%h ifid_i=%h st=%b rd=%b rpc=%h | idex: rd=%d br=%b alu_y=%h rs1f=%h rs2f=%h | wb: we=%b rd=%d d=%h",
              c, dbg_pc, dut.u_imem.mem[dbg_pc[31:2]], dut.u_cpu.ifid_instr,
              dut.u_cpu.stall, dut.u_cpu.redirect, dut.u_cpu.redirect_pc,
              dut.u_cpu.idex_rd, dut.u_cpu.idex_branch, dut.u_cpu.ex_alu_y,
              dut.u_cpu.ex_rs1_fwd, dut.u_cpu.ex_rs2_fwd,
              dut.u_cpu.wb_reg_write, dut.u_cpu.wb_rd, dut.u_cpu.wb_data);
        end
        $finish;
    end
endmodule