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Serie: RISC V Hardware armasm 112 righe · Aggiornato 2026-07-04

test_basic.s

RISC_V_Hardware/verilog/sw/test_basic.s

# ============================================================
# test_basic.s -- exercises ALU ops, immediates, lui/auipc,
# loads/stores (b/h/w, signed/unsigned), branches, jal/jalr.
# Convention: x28 (t3) collects a checksum; on success the
# program writes 0xC0DE600D to data address 0 and loops forever.
# ============================================================
start:
    # ---- arithmetic / logic ----
    li   x1, 10
    li   x2, 3
    add  x3, x1, x2        # 13
    sub  x4, x1, x2        # 7
    xor  x5, x1, x2        # 9
    or   x6, x1, x2        # 11
    and  x7, x1, x2        # 2
    sll  x8, x1, x2        # 80
    sra  x9, x1, x2        # 1
    li   x10, -16
    sra  x11, x10, x2      # -2
    srl  x12, x10, x2      # 0x1FFFFFFE
    slt  x13, x10, x1      # 1  (-16 < 10 signed)
    sltu x14, x10, x1      # 0  (0xFFFFFFF0 > 10 unsigned)

    # ---- immediates ----
    addi  x15, x1, -5      # 5
    andi  x16, x10, 0xFF   # 0xF0
    ori   x17, x7, 0x10    # 0x12
    xori  x18, x2, -1      # ~3 = 0xFFFFFFFC
    slti  x19, x10, 0      # 1
    sltiu x20, x10, 0      # 0
    slli  x21, x2, 4       # 48
    srai  x22, x10, 2      # -4

    # ---- lui / auipc ----
    lui   x23, 0xDEADB     # 0xDEADB000
    auipc x24, 0           # PC of this instruction

    # ---- memory: word / half / byte ----
    li   x25, 0x100        # base address in dmem
    li   x26, 0x12345678
    sw   x26, 0(x25)
    lw   x27, 0(x25)       # 0x12345678
    lh   x30, 0(x25)       # 0x5678
    lb   x31, 1(x25)       # 0x56
    lbu  x5,  3(x25)       # 0x12
    li   x26, 0x8000
    sh   x26, 4(x25)
    lh   x6,  4(x25)       # 0xFFFF8000 (sign-extended)
    lhu  x7,  4(x25)       # 0x00008000
    li   x26, -1
    sb   x26, 8(x25)
    lb   x8,  8(x25)       # -1
    lbu  x9,  8(x25)       # 0xFF

    # ---- branches ----
    li   x28, 0
    li   x1, 5
    li   x2, 5
    beq  x1, x2, br1
    addi x28, x28, 1       # must be skipped
br1:
    bne  x1, x2, bad
    li   x2, 6
    blt  x1, x2, br2
    addi x28, x28, 1       # skipped
br2:
    bge  x2, x1, br3
    addi x28, x28, 1       # skipped
br3:
    li   x1, -1
    li   x2, 1
    blt  x1, x2, br4       # signed: -1 < 1
    addi x28, x28, 1
br4:
    bltu x2, x1, br5       # unsigned: 1 < 0xFFFFFFFF
    addi x28, x28, 1
br5:
    bnez x28, bad          # x28 must still be 0

    # ---- loop: sum 1..10 with branch backward ----
    li   x1, 0             # sum
    li   x2, 1             # i
    li   x3, 10
loop:
    add  x1, x1, x2
    addi x2, x2, 1
    bge  x3, x2, loop
    li   x4, 55
    bne  x1, x4, bad       # sum must be 55

    # ---- jal / jalr: function call ----
    li   a0, 21
    li   a1, 21
    call func_add          # a0 = 42
    li   x4, 42
    bne  a0, x4, bad

    # ---- success ----
    li   x29, 0xC0DE600D
    sw   x29, 0(x0)        # dmem[0] = magic
halt:
    j    halt

func_add:
    add  a0, a0, a1
    ret

bad:
    li   x29, 0xDEADDEAD
    sw   x29, 0(x0)
halt2:
    j    halt2

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