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Série: RISC V Hardware verilog 37 linhas · Atualizado 2026-07-04

top_single_cycle.v

RISC_V_Hardware/verilog/rtl/top_single_cycle.v

// ============================================================
// top_single_cycle.v -- CPU + instruction ROM + data RAM
// ============================================================
`timescale 1ns/1ps

module top_single_cycle #(
    parameter MEMFILE = "program.hex"
)(
    input wire clk,
    input wire rst_n,
    output wire [31:0] dbg_pc
);
    wire [31:0] imem_addr, imem_data;
    wire        dmem_read, dmem_write;
    wire [31:0] dmem_addr, dmem_wdata, dmem_rdata;
    wire [2:0]  dmem_funct3;

    riscv_single_cycle u_cpu (
        .clk(clk), .rst_n(rst_n),
        .imem_addr(imem_addr), .imem_data(imem_data),
        .dmem_read(dmem_read), .dmem_write(dmem_write),
        .dmem_addr(dmem_addr), .dmem_funct3(dmem_funct3),
        .dmem_wdata(dmem_wdata), .dmem_rdata(dmem_rdata),
        .dbg_pc(dbg_pc)
    );

    imem #(.MEMFILE(MEMFILE)) u_imem (
        .addr(imem_addr), .instr(imem_data)
    );

    dmem u_dmem (
        .clk(clk),
        .mem_read(dmem_read), .mem_write(dmem_write),
        .addr(dmem_addr), .funct3(dmem_funct3),
        .wdata(dmem_wdata), .rdata(dmem_rdata)
    );
endmodule
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