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Chuỗi bài: RISC V Hardware armasm 65 dòng · Cập nhật 2026-07-04

test_hazard.s

RISC_V_Hardware/verilog/sw/test_hazard.s

# ============================================================
# test_hazard.s -- stress forwarding, load-use stall, branches
# Success: dmem[0] = 0xC0DE600D
# ============================================================
start:
    # ---- back-to-back RAW chain (EX/MEM and MEM/WB forwarding) ----
    li   x1, 1
    add  x2, x1, x1      # 2   (needs x1 from MEM/WB path or bypass)
    add  x3, x2, x2      # 4   (needs x2 from EX/MEM)
    add  x4, x3, x2      # 6   (x3 from EX/MEM, x2 from MEM/WB)
    add  x5, x4, x3      # 10
    li   x6, 10
    bne  x5, x6, bad

    # ---- load-use hazard (must stall 1 cycle) ----
    li   x10, 0x200
    li   x11, 77
    sw   x11, 0(x10)
    lw   x12, 0(x10)     # load
    addi x13, x12, 1     # use immediately -> stall + forward
    li   x14, 78
    bne  x13, x14, bad

    # ---- load feeding a store (data) ----
    lw   x15, 0(x10)
    sw   x15, 4(x10)     # store data needs forwarded load result
    lw   x16, 4(x10)
    bne  x16, x11, bad

    # ---- load feeding a branch ----
    lw   x17, 0(x10)
    bne  x17, x11, bad   # branch compares freshly loaded value

    # ---- branch decided by forwarded result ----
    li   x20, 5
    addi x21, x20, 5     # 10
    beq  x21, x20, bad   # not taken
    sub  x22, x21, x20   # 5
    beq  x22, x20, ok1   # taken, operand from EX/MEM
    j    bad
ok1:
    # ---- taken branch must flush wrong-path instructions ----
    li   x23, 0
    j    skip
    addi x23, x23, 1     # wrong path: must never execute
    addi x23, x23, 1
skip:
    bnez x23, bad

    # ---- jalr with forwarded base ----
    auipc x24, 0         # x24 = pc
    addi  x25, x24, 16   # target = pc+16 = 'target' below
    jalr  x26, 0(x25)    # jump there
    j     bad            # skipped
target:
    # ---- success ----
    li   x29, 0xC0DE600D
    sw   x29, 0(x0)
halt:
    j    halt
bad:
    li   x29, 0xDEADDEAD
    sw   x29, 0(x0)
halt2:
    j    halt2
← Trước

test_dbg.s

 Sau →

tb_pipeline.v

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