regfile.v

// ============================================================
// regfile.v -- 32 x 32-bit register file, x0 hardwired to 0
// 2 async read ports, 1 sync write port.
// Optional write-through bypass (BYPASS=1): a read of the
// register being written in the same cycle returns the NEW
// value. Required by the 5-stage pipeline (producer in WB,
// consumer reading in ID). Must stay 0 for the single-cycle
// core, where it would create a combinational loop.
// ============================================================
`timescale 1ns/1ps

module regfile #(
    parameter BYPASS = 0
)(
    input  wire        clk,
    input  wire        we,
    input  wire [4:0]  ra1,
    input  wire [4:0]  ra2,
    input  wire [4:0]  wa,
    input  wire [31:0] wd,
    output wire [31:0] rd1,
    output wire [31:0] rd2
);
    reg [31:0] regs [0:31];
    integer i;
    initial begin
        for (i = 0; i < 32; i = i + 1) regs[i] = 32'b0;
    end

    always @(posedge clk) begin
        if (we && (wa != 5'd0))
            regs[wa] <= wd;
    end

    wire bypass1 = (BYPASS != 0) && we && (wa != 5'd0) && (wa == ra1);
    wire bypass2 = (BYPASS != 0) && we && (wa != 5'd0) && (wa == ra2);

    assign rd1 = (ra1 == 5'd0) ? 32'b0 : (bypass1 ? wd : regs[ra1]);
    assign rd2 = (ra2 == 5'd0) ? 32'b0 : (bypass2 ? wd : regs[ra2]);
endmodule