S SmartDocs
Series: RISC V Hardware armasm 16 lines · Updated 2026-07-04

test_dbg.s

RISC_V_Hardware/verilog/sw/test_dbg.s

    li   x25, 0x100
    li   x26, 0x12345678
    sw   x26, 0(x25)
    lw   x27, 0(x25)
    lh   x30, 0(x25)
    li   x1, 0
    li   x2, 1
    li   x3, 10
loop:
    add  x1, x1, x2
    addi x2, x2, 1
    bge  x3, x2, loop
    li   x29, 0xC0DE600D
    sw   x29, 0(x0)
halt:
    j    halt
← Previous

test_basic.s

 Next →

test_hazard.s

Related articles

RISC V Hardware bash Updated 2026-07-04

build.sh

build.sh — bash source code from the RISC V Hardware learning materials (RISC_V_Hardware/build.sh).

Read article →
RISC V Hardware latex Updated 2026-07-04

style.tex

style.tex — latex source code from the RISC V Hardware learning materials (RISC_V_Hardware/latex/common/style.tex).

Read article →
RISC V Hardware verilog Updated 2026-07-04

alu.v

alu.v — verilog source code from the RISC V Hardware learning materials (RISC_V_Hardware/verilog/rtl/alu.v).

Read article →
RISC V Hardware verilog Updated 2026-07-04

branch_unit.v

branch_unit.v — verilog source code from the RISC V Hardware learning materials (RISC_V_Hardware/verilog/rtl/branch_unit.v).

Read article →
RISC V Hardware verilog Updated 2026-07-04

control.v

control.v — verilog source code from the RISC V Hardware learning materials (RISC_V_Hardware/verilog/rtl/control.v).

Read article →
RISC V Hardware verilog Updated 2026-07-04

dmem.v

dmem.v — verilog source code from the RISC V Hardware learning materials (RISC_V_Hardware/verilog/rtl/dmem.v).

Read article →