tb_pipeline.v

// ============================================================
// tb_pipeline.v -- testbench for the pipelined CPU
// ============================================================
`timescale 1ns/1ps

module tb_pipeline;
    reg clk = 0;
    reg rst_n = 0;
    wire [31:0] dbg_pc;

`ifndef MEMFILE
    `define MEMFILE "test_basic.hex"
`endif

    top_pipeline #(.MEMFILE(`MEMFILE)) dut (
        .clk(clk), .rst_n(rst_n), .dbg_pc(dbg_pc)
    );

    always #5 clk = ~clk;

    integer cycles;
    reg [31:0] result;

    initial begin
        $dumpfile("tb_pipeline.vcd");
        $dumpvars(0, tb_pipeline);
        rst_n = 0;
        repeat (2) @(posedge clk);
        rst_n = 1;

        for (cycles = 0; cycles < 4000; cycles = cycles + 1) begin
            @(posedge clk);
            result = dut.u_dmem.mem[0];
            if (result == 32'hC0DE600D) begin
                $display("PASS: magic found after %0d cycles (pc=%h)", cycles, dbg_pc);
                print_regs;
                $finish;
            end
            if (result == 32'hDEADDEAD) begin
                $display("FAIL: bad path hit after %0d cycles (pc=%h)", cycles, dbg_pc);
                print_regs;
                $fatal(1);
            end
        end
        $display("TIMEOUT after %0d cycles (pc=%h)", cycles, dbg_pc);
        print_regs;
        $fatal(1);
    end

    task print_regs;
        integer i;
        begin
            for (i = 0; i < 32; i = i + 4)
                $display("x%02d=%h x%02d=%h x%02d=%h x%02d=%h",
                    i,   dut.u_cpu.u_regfile.regs[i],
                    i+1, dut.u_cpu.u_regfile.regs[i+1],
                    i+2, dut.u_cpu.u_regfile.regs[i+2],
                    i+3, dut.u_cpu.u_regfile.regs[i+3]);
        end
    endtask
endmodule