シリーズ: RISC V Hardware
verilog
23 行
· 更新日 2026-07-04
branch_unit.v
RISC_V_Hardware/verilog/rtl/branch_unit.v
// ============================================================
// branch_unit.v -- evaluate B-type conditions from funct3
// ============================================================
`timescale 1ns/1ps
module branch_unit (
input wire [31:0] rs1,
input wire [31:0] rs2,
input wire [2:0] funct3,
output reg taken
);
always @(*) begin
case (funct3)
3'b000: taken = (rs1 == rs2); // beq
3'b001: taken = (rs1 != rs2); // bne
3'b100: taken = ($signed(rs1) < $signed(rs2)); // blt
3'b101: taken = ($signed(rs1) >= $signed(rs2)); // bge
3'b110: taken = (rs1 < rs2); // bltu
3'b111: taken = (rs1 >= rs2); // bgeu
default: taken = 1'b0;
endcase
end
endmodule
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