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シリーズ: RISC V Hardware verilog 20 行 · 更新日 2026-07-04

imem.v

RISC_V_Hardware/verilog/rtl/imem.v

// ============================================================
// imem.v -- instruction ROM, loaded from hex file
// ============================================================
`timescale 1ns/1ps

module imem #(
    parameter WORDS    = 1024,
    parameter MEMFILE  = ""
)(
    input  wire [31:0] addr,
    output wire [31:0] instr
);
    reg [31:0] mem [0:WORDS-1];
    integer i;
    initial begin
        for (i = 0; i < WORDS; i = i + 1) mem[i] = 32'h00000013; // nop
        if (MEMFILE != "") $readmemh(MEMFILE, mem);
    end
    assign instr = mem[addr[31:2]];
endmodule
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dmem.v

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imm_gen.v

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