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시리즈: RISC V Hardware bash 44 줄 · 업데이트 2026-07-04

run_tests.sh

RISC_V_Hardware/verilog/run_tests.sh

#!/bin/bash
# ============================================================
# run_tests.sh -- assemble all test programs and run them on
# both the single-cycle and the pipelined RV32I cores.
# Requires: python3, iverilog/vvp
# ============================================================
set -e
cd "$(dirname "$0")"
mkdir -p sim

RTL_COMMON="rtl/alu.v rtl/regfile.v rtl/imm_gen.v rtl/control.v rtl/branch_unit.v rtl/imem.v rtl/dmem.v"

echo "== assembling test programs =="
for s in sw/*.s; do
  base=$(basename "$s" .s)
  python3 tools/asm.py "$s" "sim/$base.hex"
done

cd sim
FAIL=0
for hex in test_basic.hex test_hazard.hex; do
  for core in single_cycle pipeline; do
    if [ "$core" = "single_cycle" ]; then
      CORE_RTL="../rtl/riscv_single_cycle.v ../rtl/top_single_cycle.v"
      TB="../tb/tb_single_cycle.v"
    else
      CORE_RTL="../rtl/riscv_pipeline.v ../rtl/top_pipeline.v"
      TB="../tb/tb_pipeline.v"
    fi
    RTL=""
    for f in $RTL_COMMON; do RTL="$RTL ../$f"; done
    echo "== $hex on $core =="
    iverilog -g2012 -o run.vvp -DMEMFILE=\"$hex\" $RTL $CORE_RTL $TB
    vvp run.vvp > run.log 2>&1 || true
    if grep -q "^PASS" run.log; then
      grep "^PASS" run.log
    else
      echo "** FAILED: $hex on $core"
      grep -E "FAIL|TIMEOUT" run.log || true
      FAIL=1
    fi
  done
done
exit $FAIL
← 이전

top_single_cycle.v

 다음 →

test_basic.s

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