module riscv_single_cycle (
    input  wire        clk, rst_n,
    output wire [31:0] imem_addr,    // -> 指令記憶體
    input  wire [31:0] imem_data,
    output wire        dmem_read, dmem_write,
    output wire [31:0] dmem_addr,    // -> 資料記憶體
    output wire [2:0]  dmem_funct3,
    output wire [31:0] dmem_wdata,
    input  wire [31:0] dmem_rdata,
    output wire [31:0] dbg_pc        // 除錯觀察
);

wire [31:0] pc_plus4      = pc + 32'd4;
wire take_branch          = branch & br_taken;
wire [31:0] branch_target = pc + imm;                  // B/J 型共用
wire [31:0] jalr_target   = (rs1_data + imm) & ~32'b1; // I 型, 清 bit0

assign pc_next = jump        ? branch_target :  // jal
                 jalr        ? jalr_target   :  // jalr
                 take_branch ? branch_target :  // beq/bne/...
                               pc_plus4;

always @(posedge clk or negedge rst_n)
    if (!rst_n) pc <= 32'b0;  else pc <= pc_next;

wire [31:0] alu_a = alu_a_pc ? pc  : rs1_data;   // auipc 用 PC
wire [31:0] alu_b = alu_src  ? imm : rs2_data;   // I/S 型用 imm

assign wb_data = (wb_sel == 2'b01) ? dmem_rdata :  // 載入
                 (wb_sel == 2'b10) ? pc_plus4   :  // jal/jalr
                 (wb_sel == 2'b11) ? imm        :  // lui
                                     alu_y;        // 其餘