Série: RISC V Hardware
verilog
45 lignes
· Mis à jour 2026-07-04
alu.v
RISC_V_Hardware/verilog/rtl/alu.v
// ============================================================
// alu.v -- RV32I ALU
// op encoding (alu_op):
// 0000 ADD 0001 SUB 0010 SLL 0011 SLT
// 0100 SLTU 0101 XOR 0110 SRL 0111 SRA
// 1000 OR 1001 AND
// ============================================================
`timescale 1ns/1ps
module alu (
input wire [31:0] a,
input wire [31:0] b,
input wire [3:0] alu_op,
output reg [31:0] y,
output wire zero
);
localparam ALU_ADD = 4'b0000;
localparam ALU_SUB = 4'b0001;
localparam ALU_SLL = 4'b0010;
localparam ALU_SLT = 4'b0011;
localparam ALU_SLTU = 4'b0100;
localparam ALU_XOR = 4'b0101;
localparam ALU_SRL = 4'b0110;
localparam ALU_SRA = 4'b0111;
localparam ALU_OR = 4'b1000;
localparam ALU_AND = 4'b1001;
always @(*) begin
case (alu_op)
ALU_ADD : y = a + b;
ALU_SUB : y = a - b;
ALU_SLL : y = a << b[4:0];
ALU_SLT : y = ($signed(a) < $signed(b)) ? 32'd1 : 32'd0;
ALU_SLTU: y = (a < b) ? 32'd1 : 32'd0;
ALU_XOR : y = a ^ b;
ALU_SRL : y = a >> b[4:0];
ALU_SRA : y = $signed(a) >>> b[4:0];
ALU_OR : y = a | b;
ALU_AND : y = a & b;
default : y = 32'b0;
endcase
end
assign zero = (y == 32'b0);
endmodule
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